CS/EE 217 GPU Architecture and Parallel Programming - Fall 2016
Course Information
- Time and Location: Tues/Thur 8:10am - 9:30am @ MSE 103
- Instructor: Daniel Wong
- Email: dwong@ece.ucr.edu
- Homepage: http://www.danielwong.org
- Office: WCH 425
- Office Hours: Tuesday 10am-11am or by appointment
- TA: Amirali Abdolrashidi
- Email: aabdo001@ucr.edu
- Office Hours: Thursday 1pm-2pm @ WCH 110 or by appointment
- Piazza (for discussions): https://piazza.com/ucr/fall2016/csee217/home
- iLearn (for assignments): ilearn.ucr.edu
Announcements
- Final Exam will be on Tuesday, December 6 11:30am-2:30pm in MSE 103
- Sign up for EE260 Winter 2017 if you're interested in learning about GPU microarchitecture in depth!
- Final Project has been posted. The default project description is available here.
- Lab 3 has been assigned. Due Tuesday, November 15
- Midterm review questions has been posted. Feel free to discuss on Piazza. I will go over as much as I can during the review class.
- Lab 2 has been assigned. Due Tuesday, November 1
- Discussion will be held this Friday (9/30) from 10:10-11am in SPR 2340
- Lab 1 has been assigned. Due Thursday, October 13
- Assignment 0 has been posted. Due Tuesday, October 4, 2016
- Welcome to CS/EE 217!
Class Syllabus
Class webpage and communication
The class webpage is located at http://danielwong.org/classes/csee217-f16.
Information, resources, and announcements related to the class will be posted to the webpage.
In addition, we will be using ilearn for assignments, and piazza for discussions and help.
Course Description
Introduces the popular CUDA based parallel programming environments based on Nvidia GPUs. Covers the basic CUDA memory/threading models. Also covers the common data-parallel programming patterns needed to develop a high-performance parallel computing applications. Examines computational thinking; a broader range of parallel execution models; and parallel programming principles.
Prerequisite: CS160 Concurrent Programming and Parallel Systems
Textbook
- Programming Massively Parallel Processors, 2nd Ed., by D. Kirk and W Hwu (primary textbook)
- CUDA by example, Sanders and Kandrot (recommended)
Grade Breakdown
- For non-research track final project:
- Labs: 35%
- Midterm and Final: 35%
- Project: 30%
- For research track final project
- Labs: 41%
- Midterm: 24%
- Project: 35%
- Class Participation and Extra Credit: 5% bonus
Project Policies
- You have 3 slip days that you can use on any lab. If you exceed your slip days, there will be a 15% penalty per late day (counting weekends). For group assignments, 1 slip day will be assessed to each group member.
- No extensions for labs will be given (see slip days). Even if you're one minute late, it will be considered late.
- All labs will be due at the end on the day (midnight).
- All labs should be uploaded to iLearn.
Policies
- You are responsible for all materials covered in lectures.
- Cheating in labs, quizzes, projects, and exams are absolutely prohibited. The minimum penalty for a violation of the regulations will be a zero for the assignment; the maximum penalty will be failure in the course.
- Examinations must be taken in class on the day they are given. There will be no exceptions.
Academic Integrity
Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: conduct.ucr.edu.
Attendance
You are expected to attend all lectures. While the slides contain all the information you need to know, some of the contents don't make sense unless you attend lecture.
Tentative Schedule
The following schedule is tentative and is subject to change. For lecture slides, you have to be logged into iLearn to download.
| Date | Topic | Assignments | Slides |
|---|---|---|---|
| Sep 22, Th | Introduction | 0-introduction.pptx Module1 |
|
| Sep 27, T | CUDA C | Assignment 0 | Module2 |
| Sep 29, Th | CUDA Parallelism | Lab 1 lab1-starter.zip | Module3 |
| Oct 4, T | CUDA Memory | Module4 | |
| Oct 6, Th | DRAM | Module6 | |
| Oct 11, T | Histogram | Module7 | |
| Oct 13, Th | Stencil | Lab 1 Due Lab 2 lab2-starter.zip | Module8 |
| Oct 18, T | Reduction | Module9 | |
| Oct 20, Th | Scan | Module10 | |
| Oct 25, T | Review | Midterm Review Midterm Solutions |
|
| Oct 27, Th | Exam 1 | Midterm solution | |
| Nov 1, T | No Class | Lab 2 Due Lab 3 lab3-starterv2.zip | |
| Nov 3, Th | Project Kickoff | Final Project Default Project Description | |
| Nov 8, T | Data Transfer | Module14 | |
| Nov 10, Th | GPGPU-sim/Architecture | Architecture | |
| Nov 15, T | Architecture (cont.) | Lab 3 Due Lab 4 (Extra Credit) lab4-starter.zip | Warp Scheduling |
| Nov 17, Th | Power | Power Gating for GPGPUs | |
| Nov 22, T | Dynamic Parallelism/ Unified Memory | Dynamic Parallelism Unified Memory |
|
| Nov 24, Th | Thanksgiving | ||
| Nov 29, T | Review | Lab 4 due | Final Exam Review |
| Dec 1, Th | No class | ||
| Dec 6, T | Exam 2 | 11:30am-2:30pm. In regular location. |