The class webpage is located at http://danielwong.org/classes/csee217-f16.
Information, resources, and announcements related to the class will be posted to the webpage.
In addition, we will be using ilearn for assignments, and piazza for discussions and help.
Introduces the popular CUDA based parallel programming environments based on Nvidia GPUs. Covers the basic CUDA memory/threading models. Also covers the common data-parallel programming patterns needed to develop a high-performance parallel computing applications. Examines computational thinking; a broader range of parallel execution models; and parallel programming principles.
Prerequisite: CS160 Concurrent Programming and Parallel Systems
Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: conduct.ucr.edu.
You are expected to attend all lectures. While the slides contain all the information you need to know, some of the contents don't make sense unless you attend lecture.
The following schedule is tentative and is subject to change. For lecture slides, you have to be logged into iLearn to download.
| Date | Topic | Assignments | Slides |
|---|---|---|---|
| Sep 22, Th | Introduction | 0-introduction.pptx Module1 |
|
| Sep 27, T | CUDA C | Assignment 0 | Module2 |
| Sep 29, Th | CUDA Parallelism | Lab 1 lab1-starter.zip | Module3 |
| Oct 4, T | CUDA Memory | Module4 | |
| Oct 6, Th | DRAM | Module6 | |
| Oct 11, T | Histogram | Module7 | |
| Oct 13, Th | Stencil | Lab 1 Due Lab 2 lab2-starter.zip | Module8 |
| Oct 18, T | Reduction | Module9 | |
| Oct 20, Th | Scan | Module10 | |
| Oct 25, T | Review | Midterm Review Midterm Solutions |
|
| Oct 27, Th | Exam 1 | Midterm solution | |
| Nov 1, T | No Class | Lab 2 Due Lab 3 lab3-starterv2.zip | |
| Nov 3, Th | Project Kickoff | Final Project Default Project Description | |
| Nov 8, T | Data Transfer | Module14 | |
| Nov 10, Th | GPGPU-sim/Architecture | Architecture | |
| Nov 15, T | Architecture (cont.) | Lab 3 Due Lab 4 (Extra Credit) lab4-starter.zip | Warp Scheduling |
| Nov 17, Th | Power | Power Gating for GPGPUs | |
| Nov 22, T | Dynamic Parallelism/ Unified Memory | Dynamic Parallelism Unified Memory |
|
| Nov 24, Th | Thanksgiving | ||
| Nov 29, T | Review | Lab 4 due | Final Exam Review |
| Dec 1, Th | No class | ||
| Dec 6, T | Exam 2 | 11:30am-2:30pm. In regular location. |