CS 203 Advanced Computer Architecture - Fall 2016

  • Time and Location: Tues/Thur 2:10pm - 3:30pm @ WCH 141
  • Instructor: Daniel Wong
    • Email: dwong@ece.ucr.edu
    • Office: WCH 425
    • Office Hours: Tuesday 10am-11am or by appointment
  • TA: Shahriyar Valielahe Roshan
    • Email: svali003@ucr.edu
    • Office Hours: Friday, 1:10pm - 2:40pm @ WCH 110 or by appointment
  • iLearn (for assignments): ilearn.ucr.edu

  • Sign up for EE260 Winter 2017 if you're interested in learning about GPU microarchitecture in depth!
  • Final Project has been assigned. Due Tuesday, December 6, 2016
  • Lab 3 has been assigned. Due Thursday, November 17, 2016
    • Extra credit for lab 3: Calculate the cold, capacity, and conflict misses for the two traces using a 512KB 4-way set associative cache with 16B block size
  • Lab 2 has been assigned. Due Sunday, October 30, 2016
  • Lab 1 has been assigned. Due Tuesday, October 18, 2016
  • Assignment 0 has been posted. Due Tuesday, October 4, 2016
  • Placement exam will be on Tuesday, September 27 in WCH 205/206.
  • Welcome to CS 203!

Class webpage and communication

The class webpage is located at http://danielwong.org/classes/cs203-f16.

Information, resources, and announcements related to the class will be posted to the webpage.

In addition, we will be using ilearn for assignments, and piazza for discussions and help.

Course Description

This graduate level course cover topics in microarchitecture such as pipelining, branch prediction, instruction-level parallelism, dynamic scheduling, speculation, memory hierarchies, and parallel architectures. This course will be project-based. Projects are designed to allow students to gain computer architecture design skills, and to reinforce topics covered from lectures.

Prerequisite: CS 161


  • (Required) Computer Architecture: A Quantitative Approach, 5th Edition By Hennessy and Patterson
  • (Optional, another great reference book) Parallel Computer Organization and Design By Dubois, Annavaram, and Stenstrom

Grade Breakdown

  • Labs: 35%
  • Final Project: 20%
  • Exam 1: 25%
  • Exam 2: 20%
  • Class Participation and Extra Credit: 5%

Project Policies

  • You have 3 slip days that you can use on any one lab or combination of labs (except the final project). If you exceed your slip days, there will be a 15% penalty per late day (counting weekends). For group assignments, 1 slip day will be assessed to each group member.
  • No extensions for labs will be given (see slip days). Even if you're one minute late, it will be considered late.
  • All labs will be due at the end the due date (midnight).
  • All labs should be uploaded to iLearn.


  • You are responsible for all materials covered in lectures.
  • Cheating in labs, quizzes, projects, and exams are absolutely prohibited. The minimum penalty for a violation of the regulations will be a zero for the assignment; the maximum penalty will be failure in the course.
  • Examinations must be taken in class on the day they are given. There will be no exceptions.

Academic Integrity

Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: conduct.ucr.edu.


You are expected to attend all lectures. While the slides contain all the information you need to know, some of the contents don't make sense unless you attend lecture. =)

The following schedule is tentative and is subject to change.

Date Topic Assignments Slides Readings
Sep 22, Th Introduction / Perf, Trends Intro
Sep 27, T Placement Exam in WCH 205/206
Sep 29, Th Trends (cont.), Reliability Assignment 0 Reliability
Oct 4, T ISA, Simulators Lab 1 Assigned ISA
Oct 6, Th Pipeline Pipelining
Oct 11, T Pipeline cont. / ILP - Static Pipelining2
Oct 13, Th ILP - Branch Prediction ILP-Branch Prediction
Oct 18, T ILP - Dynamic Lab 1 Due
Lab 2 Assigned
Tomasulo Example
Oct 20, Th ILP - Dynamic / ILP - Speculative Tomasulo Example 2
Oct 25, T ILP - Speculative Tomasulo Speculative Example
Oct 27, Th Exam Review Lab 2 Due (Oct 30, Sun) Sample Problems
Nov 1, T Exam 1 Midterm Solutions
Nov 3, Th Cache Lab 3 Assigned Cache
Nov 8, T Cache (cont.) Final Project Assigned
Nov 10, Th Memory Memory
Nov 15, T VM Virtual Memory
Nov 17, Th Multi-threading / TLP Lab 3 Due TLP
Nov 22, T Vector/GPU Vector/GPU
Nov 24, Th Thanksgiving
Nov 29, T Research Topics Research
Dec 1, Th Exam Review Final Exam Sample Problems
Dec 6, T Final Project Due
Dec 8, Th Exam 2 In WCH141 (regular classroom), 9am-11am