The class webpage is located at http://danielwong.org/classes/cs161-s16.
Information, resources, and announcements related to the class will be posted to the webpage.
In addition, we will be using ilearn for assignments, and piazza for discussions and help.
This course will show the relationship between hardware and software and focus on computer architecture and design. Topics include instruction set architecture, processor data path design and pipelining, and memory hierarchies.
Prerequisite: CS 120A or EE 120A Co-requisite: CS161L
Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: conduct.ucr.edu.
You are expected to attend all lectures. While the slides and readings contain all the information you need to know, some of the contents won't make sense unless you attend lecture.
The following schedule is tentative and is subject to change.
| Lecture | Date | Topic | Assignments | Slides | Readings |
|---|---|---|---|---|---|
| 1 | Mar 29, T | Intro/Trends/Performance | Assignment 0 | 1.1-1.11 Due 4/5 |
|
| 2 | Mar 31, Th | ISA | 2.1-2.20 | ||
| 3 | Apr 5, T | ISA | Assignment 1 Solution (iLearn) | 2.1-2.20 | |
| 4 | Apr 7, Th | ISA | 2.1-2.20 Due 4/12 |
||
| 5 | Apr 12, T | Single cycle | 4.1-4.4 | ||
| 6 | Apr 14, Th | Single cycle | 4.1-4.4 | ||
| 7 | Apr 19, T | Single cycle | Assignment 2 Solution (iLearn) | 4.1-4.4 Due 4/19 |
|
| 8 | Apr 21, Th | Multi cycle | 5.1-5.6 | ||
| 9 | Apr 26, T | Multi cycle | 5.1-5.6 Due 4/26 |
||
| 10 | Apr 28, Th | Review | |||
| 11 | May 3, T | Midterm | Midterm Solution | ||
| 12 | May 5, Th | Pipeline | 6.1-6.11 | ||
| 13 | May 10, T | Pipeline | Assignment 3 | 6.1-6.11 | |
| 14 | May 12, Th | Pipeline | 6.1-6.11 Due 5/17 |
||
| 15 | May 17, T | Cache | 7.1-7.6 | ||
| 16 | May 19, Th | Cache | 7.1-7.6 | ||
| 17 | May 24, T | VM | Assignment 4 | 8.1-8.2 | |
| 18 | May 26, Th | Main Memory | |||
| 19 | May 31, T | Reliability/Review | Cache Examples VM Examples More Examples | ||
| 20 | June 2, Th | Class Cancelled | |||
| 21 | June 9, Thur | Final Exam | 8am - 11am |